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September 15, 2021
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Wednesday, September 15 • 7:45am - 8:05am
An Efficient Implementation of TensorFlow Lite for RISC-V Vectors - Mostafa Hagog, SiFive

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When deploying a neural network (NN) as part of a low-power edge application such as mobile or IoT devices, designers must trade-off flexibility and power efficiency. Hard-wired accelerators are often chosen for their inherent parallelism and performance; however, accelerators are rigid, may be difficult to program, and are not necessarily suited for some NNs that can’t take advantage of the parallelism provided. Conversely, general-purpose processors, ubiquitous in edge applications, may lack the compute efficiency needed under a strict power budget. A third option is a processor, optimized for parallelizable workloads, that can scale to many-core to deliver the necessary performance of multiple tera-ops per second that machine learning algorithms may require. Consequently, demand for vector-enabled, general-purpose processors that are compiler-friendly is rapidly growing. Using the widely deployed MobileNet CNN as an example, SiFive will demonstrate a TensorFlow Lite solution optimized for RISC-V vectors and then further boosted by more than 10X in some cases with SiFive Intelligence Extensions.

avatar for Mostafa Hagog

Mostafa Hagog

VP Software, SiFive
Mostafa Hagog is an industry veteran leader in developing AI acceleration, having previously worked with Nvidia and Intel. Mostafa has contributed to the AVX instruction set architecture, and gnu open-source compiler project. Mostafa has a M.Sc in Electrical Engineering.

Wednesday September 15, 2021 7:45am - 8:05am PDT
  • Slides Attached Yes